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cy5057 high-frequency flash programmable pll die with spread spectrum cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07363 rev. *i revised march 21, 2011 features flash programmable die for in-package programming of crystal oscillators high resolution phase-locked lo op (pll) with 10-bit multiplier and 7-bit divider flash programmable capacitor tuning array simple two-pin programming interface (excluding vdd and v ss pins) on-chip oscillator used with external 25.1 mhz fundamental tuned crystal flash programmable spread spectrum with spread percentages between 0.25% and 2.00% spread spectrum on/off function operating frequency: 5 mhz to 170 mhz at 3.3 v 10% seven-bit linear post divider with divide options from divide-by-2 to divide-by-127 programmable pd# or oe pin programmable asynchronous or synchronous oe and pd# modes low jitter output: < 200 ps (pk-pk) at 3.3 v 10% controlled rise and fall times and output slew rate software configuration support benefits enables quick turnaround of cu stom oscillators and lowers inventory costs through stocking blank parts. in addition, the part may be flash programmed up to 100 times. this reduces programming errors and provides an easy upgrade path for existing designs. enables synthesis of highly accurate and stable output clock frequencies with zero or low ppm. enables fine tuning of output clock frequency by adjusting the load capacitance of the crystal. allows the device to go into standard 4 or 6-pin packages. lowers cost of oscillator, because pll may be programmed to a high frequency using a low frequency, low cost crystal. provides various spread percentage. provides the ability to enable or disable spread spectrum with an external pin. provides flexibility in output configurations and testing. enables low power operation or output enable function. provides flexibility for system ap plications through selectable instantaneous or synchronous change in outputs. suitable for most pc, consumer, and networking applications. has lower emi than oscillators. easy to use software support for design entry. crystal osc with 8-bit cap array xin xou t 7-bit q 100- to 400-mhz pll 7-bit output divider block out pd#/oe flash configuration/ spread spectrum storage 10-bit p spread spectrum sson# logic block diagram [+] feedback
cy5057 document #: 38-07363 rev. *i page 2 of 11 die pad figure 1. die pad diagram note active die size: x = 75.0 mils / 1907 m bond pad opening: 85 m x 85 m pad pitch: 125 m x 125 m (pad center to pad center) y = 56.2 mils / 1428 m scribe: x (vertical) = 3.4 mils / 86.2 m y (horizontal) = 2.8 mils / 71 m wafer thickness: 11 mils typical table 1. die pad definitions [pad coordinates are referenced from th e center of the die (x = 0, y = 0)] name die pad description x coordinate y coordinate v dd 1,2 power supply ?843.612 597.849, 427.266 v ss 6,7 ground 883.743, 887.355 ?563.304, ?369.957 xin 4 crystal gate pin ?843.612 ?1.806 xout 3 crystal drain pin ?843.612 236.565 pd#/oe 5 flash programmable to function as power down or output enable in normal operating mode. weak pull up is enabled by default. ?843.612 ?424.662 v pp super voltage when going into programming mode. sda data pin when going into and when in programming mode. sson# 10 active low spread spectrum control. asserti ng low turns the internal modulation waveform on. strong pull down is enabled by default. pull down is disabled in power down mode. 834.183 589.848 scl clock pin in programming mo de. must be double bonded to the out pad for pinouts not using the sson# function. there is an internal pull down resistor on this pad. out 9 clock output. there is an internal pull down resistor on this pad. weak pull down is enabled by default. default output is from the reference. 834.183 462.840 nc 8 no connect pin (do not connect this pad). 834.183 335.832 [+] feedback
cy5057 document #: 38-07363 rev. *i page 3 of 11 functional description cy5057 is a flash programmable, high accuracy, pll-based die designed for the crystal oscillator market. it also contains spread spectrum circuitry that is enab led or disabled with an external pin. the die is integrated with a low cost 25.1 mhz fundamental tuned crystal in a 4 or 6-pin through hole or surface mount package. the oscillator devices may be stocked as blank parts and custom frequencies programm ed in-package at the last stage before shipping. this enables faster manufacturing of custom and standard crystal oscillators without the need for dedicated and expensive crystals. cy5057 contains an on-chip oscillator and unique oscillator tuning circuit for fine tuning the output frequency. the crystal c load is selectively adjusted by programming a set of flash memory bits. this feature is us ed to compensa te for crystal variations or to obtain a more accurate synthesized frequency. cy5057 uses a simple two-pin programming interface, excluding the v ss and v dd pins. . clock outputs are generated from 5 mhz to 170 mhz at 3.3 v 10% operating voltage. you can reprogram the entire flash configuration multiple times to alter or reuse the programmed inventory. cy5057 pll die is designed for very high resolution. it has a 10-bit feedback counter multiplie r and a 7-bit reference counter divider. this enables the synthesis of highly accurate and stable output clock frequencies with zero or low ppm error. the output of the pll or the oscillator is further modified by a 7-bit linear post divider with a total of 126 divider options (2 to 127). cy5057 also contains flexible power management controls. these parts include both power down mode (pd# = 0) and output enable mode (oe = 1). the power down and output enable modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enables cy5057 to have low jitter and accurate outputs. this makes it suitab le for most pc, networking, and consumer applications. cy5057 also has an additional sp read spectrum feature that is disabled or enabled with an external pin. for more information, refer the section spread spectrum . flash configuration and spread spectrum storage block ta b l e 2 summarizes the features configurable by the flash memory bits. refer to ?cy5057 programming specification? for programming details. the specification can be obtained from your cypress factory representative. pll output frequency cy5057 contains a high resolution pll with a 10-bit multiplier and a 7-bit divider. the output frequency of the pll is determined by the following equation: in this equation: q l is the loaded or programmed reference counter value (q counter) p bl is the loaded or programmed feedback counter value (p counter) po is the p offset bit (is only 0 or 1) in spread spectrum mode, the time averaged p value is used to calculate the average frequency. power management features cy5057 contains flash progra mmable pd# (active low) and oe (active high) functions. if power down mode is selected (pd# = 0), the oscillator and pll are placed in a low supply current standby mode and the ou tput is tri-stated and weakly pulled low. the oscillator and pll circuits must relock when the part leaves power down mode. if output enable mode is selected (oe = 0), the output is tri-stated and weakly pulled low. in this mode, the oscillator and pll circuits continue to operate allowing a rapid return to normal operation when the output is enabled. in addition, the pd# and oe modes may be programmed to occur synchronously or asynchronously with respect to the output signal. when the asynchronous setting is used, the power down or output disable occurs immediately (allowing for logic delays) irrespective of the position in the clock cycle. however, when the synchronous setting is used, the part waits for a falling edge at the output before power do wn or output enable signal is initiated. this prevents output glitches. in asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the nex t falling edge of the output. spread spectrum cy5057 contains spread spec trum with flash programmable spread percentage and modulation frequency. center spread nonlinear ?hershey kiss? modulation is obtained. spread percentage is programmed to values between 0.25% and 2.00%, in 0.25% intervals. on ly one spread profile (for one specific percentage spread and for one output frequency) may be programmed into the device at a time. cy5057 has a spread spectrum on and off function. the spread spectrum is enabled or disabled through an external pin. timing this feature is explained in the section switching waveforms on page 7. table 2. flash programmable features adjust frequency feedback counter value (p) reference counter value (q) output divider selection oscillator tuning (load capacitance values) oscillator direct output power management mode (oe or pd#) power management timing (synch ronous or asynchronous) spread spectrum pull up and pull down resistors f pll 2p bl 4 + () po + ? q l 2 + () --------------------------------------------- - f ref ? = equation (1) [+] feedback
cy5057 document #: 38-07363 rev. *i page 4 of 11 figure 2. crystal oscillator tuning circuit inkless die pick map (dpm) format cypress ships inkless wafe rs to customers with an accompanying die pick map, which is used to determine the good die for assembly and programming. customers can also access individual dpm files at their convenience through ftp.cypress.com with a valid user account login and password. contact your local cypress field application engineer (fae) or sales representative for a cust omer ftp account. the dpm files are named using the fab lot number and wafer number scribed on the wafer. the dpm files are transferred to the ftp account of the customer when the fact ory ships out the wafers against their purchase order (po). xout xin c xi n c xout c0 c1 c2 c3 c4 c5 c6 c7 c7 c6 c5 c4 c3 c2 c1 c0 rf table 3. crystal oscillator tuning cap values bit [1] capacitance per bit (pf) c 7 (msb) 24.32 c 6 12.16 c 5 6.08 c 4 3.04 c 3 1.52 c 2 0.76 c 1 0.38 c 0 (lsb) 0.19 note 1. c xin, c xout, and parasitic capacitance due to fixture and package must be included when calculating the total capacitance. [+] feedback
cy5057 document #: 38-07363 rev. *i page 5 of 11 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. supply voltage .................................................. ?0.5 to 7.0 v input voltage ............................................?0.5 v to v dd + 0.5 storage temperature (noncondensing) ......... ?55 c to 125 c junction temperature................................... ?40 c to 125 c data retention at tj = 125 c..................................> 10 years maximum non volatile programmi ng cycles...... ............ ....100 static discharge voltage.......................................... > 2000 v (per mil-std-883, method 3015) output (pad 9) sink or sources current ........20 ma maximum operating conditions parameter description min max unit v dd supply voltage (3.3 v) 3.0 3.6 v t aj [2] operating temperatur e, junction ?40 100 c c lc maximum capacitive load on th e output (cmos levels spec) v dd = 3.0 v to 3.6 v, output frequency = 5 mhz to 170 mhz ?15pf x ref reference frequency with spread spectrum disabled. fundamental tuned crystals only 25.1 25.1 mhz c in input capacitance (except crystal pins) ? 7 pf c xin crystal input capacitance (all internal caps off) 10 14 pf c xout crystal output capacitance (all internal caps off) 10 14 pf t psrt power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.005 500 ms dc electrical characteristics (tj = -40 to 100c) parameter description test conditions min max unit v il input low voltage pd#/oe and sson# pins v dd = 3.0 v?3.6 v ? 0.3*v dd v v ih input high voltage pd#/oe and sson# pins v dd = 3.0 v?3.6 v 0.7*v dd ?v v ol output low voltage, out pin v dd = 3.0 v?3.6 v, i ol = 8 ma ? 0.4 v v oh output high voltage, cmos levels v dd = 3.0 v?3.6 v, i oh = ?8 ma v dd ? 0.4 ? v i ilpdoe input low current, pd#/oe pin v in = v ss (internal pull up = 3 m typical) ?10 a i ihpdoe input high current, pd#/oe pin v in = v dd (internal pull up = 100 k typical) ?10 a i ilsr input low current, sson# pin v in = v ss (internal pull down = 100 k typical) ?10 a i ihsr input high current, sson# pin v in = v dd (internal pull down = 100 k typical) ?50 a i dd supply current no load, v dd = 3.0 v?3.6 v, fout = 170 mhz ? 50 ma i oz output leakage current, out pin v dd = 3.0 v?3.6 v, outp ut disabled with oe ? 50 a i pd standby current v dd = 3.0 v?3.6 v, device powered down with pd# ?50 a r up pull up resistor on pd#/oe pin v dd = 3.0 v?3.6 v, measured at v in =v ss v dd = 3.0 v?3.6 v, measured at v in = 0.7 v dd 1 80 6 150 m k r dn pull down resistor on sson# and out pins v dd = 3.0 v?3.6 v, measured at v in = 0.5 v dd 80 150 k rf crystal feedback resistor v dd = 3.0 v?3.6 v, measured at x in = 0 100 ? k [+] feedback
cy5057 document #: 38-07363 rev. *i page 6 of 11 ac electrical characteristics (tj = ?40 to 100c) parameter [2] description test conditions min max unit f out output frequency v dd = 3.0 v?3.6 v, c l = 15 pf 5 170 mhz tr out rise time v dd = 3.0 v?3.6 v, 20% to 80% v dd, c l = 15 pf ? 2.7 ns tf out fall time v dd = 3.0 v?3.6 v, 80% to 20% v dd, c l = 15 pf ? 2.7 ns dc out duty cycle divider output, measured at v dd /2 crystal direct output, measured at v dd /2 45 40 55 60 % % t j1 peak-to-peak period jitter f out > 133 mhz, v dd /2, ss off ? 200 ps 25 mhz < f out < 133 mhz, v dd /2, ss off 400 ps f out < 25 mhz, v dd /2, ss off 1% of 1/f out s t j2 cycle-to-cycle jitter f out >133 mhz, v dd /2, ss on ? 200 ps 25 mhz < f out < 133 mhz, v dd /2, ss on 400 ps f out < 25 mhz, v dd /2, ss on 1% of 1/f out s f mod modulation frequency 30 33 khz dl crystal drive level measured at 25.1 mhz, with crystal esr = 20 , cap setting = hex16, dl = program code [1,0] ?540 w ?r negative resistance measured at 25.1 mhz, cap setting = hex 3f ? ?200 note 2. in cypress standard tssop packages with external crystal. timing parameters parameter [2] description min max unit t sson1 time from steady state spread to steady state nonspread -- 600 s t sson2 time from steady state non spre ad to steady state spread -- 100 s t sson3 minimum sson# pulse width (positive or negative) 250 ? s t mod spread spectrum modulation period 30 33.33 s t stp,sync time from falling edge on pd# to stopped outputs, synchronous mode, t = 1/f out -- 1.5t + 350 ns t stp,async time from falling edge on pd# to stopped outputs, asynchronous mode -- 350 ns t pu,sync time from rising edge on pd# to outputs at valid frequency, synchronous mode -- 3 ms t pu,async time from rising edge on pd# to outputs at valid frequency, asynchronous mode -- 3 ms t pxz,sync time from falling edge on oe to high impedance outputs, synchronous mode, t = 1/f out -- 1.5t+350 ns t pxz,async time from falling edge on oe to high impedance outputs, asynchronous mode -- 350 ns t pzx,sync time from rising edge on oe to running outputs, synchronous mode, t=1/f out -- 1.5t + 350 ns t pzx,async time from rising edge on oe to running outputs, asynchronous mode -- 350 ns t lock pll lock time (from 0.9 v dd to valid output clock frequency) -- 10 ms [+] feedback
cy5057 document #: 38-07363 rev. *i page 7 of 11 switching waveforms figure 3. duty cycle timing (dc) figure 4. output rise/fall time figure 5. power down timing (synchronous and asynchronous modes) figure 6. output enable timing (synchronous and asynchronous modes) t 1a t 1b duty t 1a t 1b ------- - 100% [] = output output t r v dd 0 v t f high impedance weakly pulled low high impedance weakly pulled low v dd power down (pd#) v il v ih t stp t pu clkout (synchronous) clkout (asynchronous) t stp t pu high impedance weakly pulled low high impedance weakly pulled low v dd output enable (oe) clkout (synchronous) clkout (asynchronous) v il v ih t pxz t pzx t pxz t pzx [+] feedback
cy5057 document #: 38-07363 rev. *i page 8 of 11 figure 7. power up timing figure 8. spread spectrum on and off timing ordering code definitions ordering information ordering code status type operating range CY5057-11WAF-IL active inkless wafer (background to 11 mils) ?40 c to 100 c clkout power up valid clkout v dd 0v 0.9v dd t psrt t lock +100% -100% internal modulation waveform sson# t sson2 t sson1 t sson3 0% cy5057 base part number -11waf wafer background to 11 mils inkless -il [+] feedback
cy5057 document #: 38-07363 rev. *i page 9 of 11 acronyms document conventions units of measure acronym description clkout clock output cmos complementary metal oxide semiconductor dpm die pick map emi electromagnetic interference eprom erasable programmab le read only memory fae field application engineer ftp file transfer protocol oe output enable pal phase alternate line pd power down pll phase locked loop ppm parts per million tssop thin shrunk small outline package ttl transistor transistor logic symbol unit of measure c degrees celsius ma milli amperes mm milli meters ms milli seconds ns nano seconds ps pico seconds ppm parts per million ohms k kilo ohms mhz mega hertz m mega ohms a micro amperes f micro farads m micro meters pf pico farads pp peak-to-peak vvolts % percent [+] feedback
cy5057 document #: 38-07363 rev. *i page 10 of 11 document history page document title: cy5057 high-frequency flash programmable pll die wi th spread spectrum document number: 38-07363 revision ecn orig. of change submission date description of change ** 112486 ckn see ecn new data sheet *a 121373 ckn see ecn added scribe lines to die pad description added wafer thickness to die pad description added x and y coordinates to die pad description removed list of discrete frequencie s and discrete spread percentages removed references to discrete frequencies and profile tables replaced with description of software for full programmability operating frequency changed to 5 mhz?170 mhz removed c0 and c1 from crystal oscillator tuning circuit; renumbered other capacitors changed maximum junction temperature to 125c changed pdoe internal pull up value to 1?6 mohm when v in = v ss changed iilpdoe to 10 a changed rf spec to 100 kohm, at condition x in = 0 change dl spec to 540 w, at condition cap setting = hex16, dl=10 added power up timing diagram separate from power down timing diagram removed die information table *b 127414 rgl see ecn added ?11 and other details to ordering information added t pu details to operating conditions changed max t sson1 value to 600 in timi ng parameters table changed parameter t pu under timing parameters to t lock with the description ?pll lock time? altered minimum and maximum values in power up timing figure *c 2143928 fga/pyrs see ecn modified power down timing diagram changed power up timing from min. of 50 s to 5 s added output sink/source current specification in the absolute max ratings change cap array from 10 to 8-bit add msb and lsb in the crystal oscillator tuning cap values table fixed power up timing diagram added -r cap setting value ff added inkless die information before absolute maximum ratings added new part number (c y5057-11waf-il) with note *d 2541797 aesa 07/24/08 updated template. added note ?not recommended for new designs.? added part number cy5057k-11waf-il in ordering information table. *e 2600816 kvm/aesa 11/04/08 updated to match data sheet labeled ?rev *c november 16, 2004? (added logo and die number to die drawing; added pull up & pull down resistors to features table; revised ?r spec and conditions; added missing labels to waveform drawings) removed cy5057k-11waf-il from ordering information table. updated die dimensions (page 2) with 29 mil thickness; corrected scribe variables *f 2621902 kvm/aesa 12/15/2008 corrected ty pos on p. 1 (spread amount) & p. 5 (v il & v ih test conditions). connected text frames. *g 2897373 cxq 03/22/10 removed part number cy5057- 29waf-il from ordering information table. updated copyright section. *h 3068367 cxq 10/21/2010 remov ed cy5057-11waf part from ordering information . added ordering code definitions . *i 3201346 cxq 03/21/2011 sunset review. no material changes to document. fixed various typos. included acronyms and units tables. updated template and styles. [+] feedback
document #: 38-07363 rev. *i revised march 21, 2011 page 11 of 11 all products and company names mentioned in this document may be the trademarks of their respective holders. cy5057 ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of of fices, solution centers, ma nufacturers? representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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